Smart field data devices in use today are generally Highway Addressable Remote Transducer (HART) enabled devices. HART is a global standard for sending and receiving digital information across analog wires between smart devices and control or monitoring systems. The HART communications protocol is widely recognized as the industry standard for digitally enhanced 4 milliamperes (mA) to 20 mA smart instrument communication. Use of HART based technology is growing rapidly and most major global instrumentation suppliers offer products with the HART communications protocol. The HART communications protocol enables two-way digital communication with smart instruments without disturbing 4 mA-20 mA analog signals. The HART communications protocol utilizes, for example, the Bell 202 frequency shift keying (FSK) standard of the Bell 202 modulator-demodulator (modem) of Bell System to superimpose digital communication signals at a low level over the 4 mA-20 mA analog signals. HART technology enables two-way field communication and makes it possible for additional information beyond typical process variables to be communicated to and from a smart field instrument. Current deployment of HART field data devices, that is, smart field data devices that support the HART protocol, utilize a hardware based Bell 202 modem at 1200 bits per second and a separate microcontroller for an implementation of the HART communications protocol. There are a number of hardware based modems that use a Bell 202 based modulation scheme, available in the industry. A HART field data device comprises a microcontroller, a HART modem, and an interface arrangement compliant to a conventional 4 mA-20 mA current loop circuit. The HART modem supporting the HART FSK protocol demodulates a non-coherent HART FSK signal by mixing the non-coherent HART FSK signal with a free running oscillator, that is, a carrier signal, and then identifies a phase of a resultant signal. The total component count of the HART modem to perform both modulation and demodulation adds to the overall cost, lowers reliability of the HART modem, and results in high power consumption.
In 2001, the Highway Addressable Remote Transducer (HART) Communication Foundation (HCF) published a high speed HART (HSH) communication protocol at 9600 bits per second speed using a coherent 8-ary phase shift keying (C8PSK) modulation and demodulation scheme. The HSH communication protocol, that is, the HART C8PSK protocol caters for increasing the number of transactions between HART field data devices and control and monitoring systems to realize multiple control functions of the HART field data devices. A physical layer specification of the HART C8PSK protocol specifies that physical device type, message structure, and network configuration rules of the HART C8PSK protocol are same as the physical layer specification of the HART frequency shift keying (FSK) protocol. That is, the HART field data devices can communicate using the HART C8PSK protocol and/or the HART FSK protocol. The HART field data devices employ a modem that functions for both the HART C8PSK protocol and the HART FSK protocol. The analog signals transmitted and received by the HART field data devices are HART C8PSK analog signals or HART FSK analog signals.
FIG. 1 (Prior Art) exemplarily illustrates a typical Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) modulator 100 comprising a C8PSK gray coder 101, raised cosine filters 102 and 103, and mixers 104, 105, and 106, for modulating an analog signal comprising a HART message transmitted by HART field data devices, that is, sensor devices in a field environment. The C8PSK gray coder 101 receives a serial data bit stream obtained on sampling of an analog signal output by the HART field data devices. The C8PSK gray coder 101 divides the received serial data bit stream into symbols comprising three consecutive bits of the serial data bit stream and maps each of the symbols to a phase angle. The C8PSK gray coder 101 also maps each of the phase angles to a corresponding in-phase component and a quadrature phase component. The HART C8PSK specifications further require that the in-phase component and the quadrature phase component be shaped using 50% raised cosine filters 102 and 103 to achieve minimal inter symbol interference. The in-phase component of each of the symbols is shaped through the raised cosine filter 102 and the quadrature phase component of each of the symbols is shaped through another raised cosine filter 103. The raised cosine filters 102 and 103 output an in-phase (I) signal and a quadrature phase (Q) signal corresponding to each of the symbols. The I signal and the Q signal are modulated using a carrier signal of frequency of, for example, 3200 hertz (Hz). The modulation comprises generating a HART C8PSK analog signal by multiplying the resulting output I signal of the raised cosine filter 102 by cos(wct) to obtain a first product and subtracting a second product of the output Q signal of the raised cosine filter 103 and sin(wct) from the first product using the mixers 104, 105, and 106. The HART C8PSK analog signal is represented below:X(t)=I cos(wct)−Q sin(wct)
Consider an example where an output sample rate of the Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) analog signal of 25600 Hz is desired from the HART C8PSK modulator 100. For this output sample rate, the raised cosine filters 102 and 103, for example, finite impulse response filters in the HART C8PSK modulator 100 require 17 filter taps. Thus, the raised cosine filters 102 and 103 for the in-phase component and the quadrature phase component respectively, require 17 multiplications and 17 additions each. Further, the in-phase (I) signal and the quadrature phase (Q) signal require 2 more multiplications and an addition each in the mixers 104, 105, and 106. For transmitting one sample of the HART message in the carrier signal, the HART C8PSK modulator 100 involves 36 multiplications and 35 additions. Thus, for an output sample rate of the HART C8PSK analog signal of 25600 Hz, the HART C8PSK modulator 100 performs 921600 multiplications and 896000 additions. All these computations require large computing resources thus making it difficult to meet low power requirements of the HART C8PSK modulator 100 in transmission of analog signals. Therefore, there is a need for a HART C8PSK modem that performs modulation of the received analog signals with low power consumption.
FIG. 2 (Prior Art) exemplarily illustrates a demodulator 200 of a multi-speed Highway Addressable Remote Transducer (HART) (MSH) modem jointly developed by industry majors such as Rosemount Inc., SMAR, Siemens Inc., and the HART Communication Foundation (HCF). The MSH modem comprises a modulator and the demodulator 200. To achieve power efficiency, both the modulator and the demodulator 200 of the MSH modem need to be optimized for power and performance. The demodulator 200 exemplarily illustrated in FIG. 2, is initialized as an incoming signal is a HART coherent 8-ary phase shift keying (C8PSK) analog signal even though the demodulator 200 can classify the incoming signal as a frequency shift keying (FSK) signal and demodulate the FSK signal. The demodulator 200 comprises band pass filters 201 and 213, an automatic gain control circuit 202, an analog-to-digital converter (ADC) 203, a direct current filter 204, mixers 205 and 206, a numerically controlled oscillator 207, a root raised cosine filter 208, an equalizer 209, squaring circuits 210 and 211, a summing circuit 212, a peak detector 214, an interpolator 215, a phase shift keying (PSK) decision module 216, an angle error detector 217, a phase locked loop filter 219, and a frequency shift keying (FSK) decision module 218. The band pass filter 201 filters the incoming signal. The automatic gain control circuit 202 adjusts gain of the incoming signal. The ADC 203 digitizes and converts the gain adjusted signal to digitized samples. The direct current filter 204 smoothens ripples in the digitized samples. In-phase components and quadrature phase components corresponding to the digitized samples are generated using the numerically controlled oscillator 207, the mixers 205 and 206, and the root raised cosine filter 208. The root raised cosine filter 208 is a pulse shaping filter for pulse shaping the generated in-phase components and the generated quadrature phase components to generate in-phase signals and quadrature phase signals. The root raised cosine filter 208 also functions as a low pass filter to remove unwanted high frequencies in the generated in-phase components and the generated quadrature phase components.
The equalizer 209 receives the outputs of the root raised cosine filter 208 and generates delayed in-phase signals and delayed quadrature phase signals that are fed as inputs to a symbol synchronization circuit comprising a pair of squaring circuits 210 and 211. The squaring circuits 210 and 211 square the delayed in-phase signals and the delayed quadrature phase signals and the summing circuit 212 sums the result to produce a demodulated analog signal that is filtered by the band pass filter 213. The peak detector 214 detects peaks of the demodulated analog signal that correspond to sampling time instants of the Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) analog signal that is sampled by the analog-to-digital converter (ADC) 203. The outputs of the equalizer 209 are fed to the interpolator 215 and the angle error detector 217. The interpolator 215 selects a digitized sample of the HART C8PSK analog signal that is to be unmapped and decoded to a symbol with binary bits by the phase shift keying (PSK) decision module 216. The angle error detector 217 identifies the protocol of the incoming signal, that is, whether the incoming signal is a frequency shift keying (FSK) signal or a C8PSK analog signal.
For demodulating the Highway Addressable Remote Transducer (HART) frequency shift keying (FSK) analog signals, the multi-speed HART (MSH) modem uses the equalizer 209 configured as an adaptive equalizer to compensate for cable losses in transmission since the HART FSK signals slightly distort during the transmission. For coherent demodulation of the HART coherent 8-ary phase shift keying (C8PSK) analog signal as per the physical layer specification of the HART C8PSK protocol, the demodulator 200 provides the automatic gain control (AGC) circuit 202, the root raised cosine filter 208, the symbol synchronization circuit, the equalizer 209, the angle error detector 217, and the phase locked loop filter 219 for carrier recovery and signal identification by the phase shift keying (PSK) decision module 216 and the FSK decision module 218 as exemplarily illustrated in FIG. 2. With the additional components to cater for identification and demodulation of both the HART FSK analog signal and the HART C8PSK analog signal, the MSH modem has low reliability with high power consumption. The high power consumption in the demodulator 200 because of the number of multiplications used per symbol demodulation, and multipliers of the demodulator 200 also result in a large area in the MSH modem. Total worst case current is substantially high, more than about 2 mA. Therefore, there is a need for a HART C8PSK modem that performs demodulation of received analog signals with low power consumption.
FIG. 3 (Prior Art) exemplarily illustrates a block diagram of a low power demodulator 300 of a multi-speed Highway Addressable Remote Transducer (HART) (MSH) modem. The low power demodulator 300 receives an incoming signal. The incoming signal is assumed to be a frequency shift keying (FSK) signal and the low power demodulator 300 is accordingly configured. The low power demodulator 300 comprises a band pass filter 301, a variable gain amplifier 302, an analog-to-digital converter (ADC) 303, a direct current filter 304, an automatic modulation classifier and automatic gain control circuit 305, a mixed lookup table 306, a root raised cosine filter lookup table 307, an interpolator 308, a coordinate rotation digital computer (CORDIC) 309, an equalizer adder array 310, a synchronizer tracker 311, a phase shift keying (PSK) decision module 312, an FSK decision module 314, a filter 315, and an output switch 316. The band pass filter 301 filters the incoming FSK signal. The variable gain amplifier 302 adjusts gain of the filtered FSK signal. The ADC 303 digitizes the gain adjusted FSK signal. The direct current filter 304 filters the digitized FSK signal. The automatic modulation classifier and the automatic gain control circuit 305 perform automatic modulation classification and automatic gain control. The automatic modulation classifier determines that the digitized samples of the gain adjusted signal are in the FSK protocol and demodulates the digitized samples using the mixer lookup table 306 and the raise cosine filter lookup table 307. Based on the sign 313 of the generated in-phase signal and the generated quadrature phase signal, the FSK decision module 314 outputs demodulated data through the output switch 316 via the filter 315 after carrier recovery. If the automatic modulation classifier determines that the digitized samples of the gain adjusted signal are in the coherent 8-ary phase shift keying (C8PSK) protocol, the interpolator 308, the CORDIC 309, and the equalizer adder array 310 in coordination with the synchronizer tracker 311 perform timing estimation of the digitized samples of the incoming C8PSK signal to output demodulated digitized samples. The equalizer adder array 310 initializes the synchronizer tracker 311 for a preamble of the HART message in the incoming C8PSK signal and functions as a fixed single preset equalizer that adapts to actual line conditions, that is, the digitized samples of the incoming C8PSK signal present in the low power demodulator 300 after initialization of the synchronizer tracker 311 is complete. Theoretically and in simulations, the low power demodulator 300 functions in accordance with requirements. In the low power demodulator 300 exemplarily illustrated in FIG. 3, the phase of the incoming C8PSK signal is estimated using the following equations:SumQ(m)=Σ16n=1 Q(n+m)SumI(m)=Σ16n=1 I(n+m)Ti(m)=Σ8n=1 I(n+m)−Σ15n=8 I(n+m)SumQ(m)=A cos(Δθ)SumI(m)=A sin(Δθ)
where Δθ is a carrier phase error and is defined as Δθ=45*k+m, Q(n) is a quadrature phase component of the digitized samples of the received HART C8PSK analog signal, and I(n) is an in-phase component of the digitized samples of the received HART C8PSK analog signal. The resulting SumQ(m) and SumI(m) go through the phase shift keying (PSK) decision module 312, which judges the function parameter k and a lookup table of an abstract value SumQ(m) is used to compute m.
The low power demodulator 300 requires sampling of the received Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) analog signal at 8 times a baud rate of 3200 resulting in a substantially high sampling rate of more than 25 kilohertz (KHz). Another requirement of the multi-speed HART (MSH) modem is to get the low power demodulator 300 in an optimum detection range within a period of 40 symbols or bauds. To achieve this, a fast detection of an incoming phase of the received HART C8PSK analog signal and an estimation of a center point timing of an impulse response, that is, a I/Q waveform of root raised cosine filters in the low power demodulator 300 must be performed. Using the above equations, the low power demodulator 300 requires a substantially high sample rate of 25600 Hz to achieve the above recited requirement. To arrive at an accurate phase error estimate and an estimate of a timing offset, the low power demodulator 300 requires the high sample rate of 25600 Hz. The computing requirements of a processor of the MSH modem increase 2 times despite avoiding the use of multipliers. Moreover, the number of computing cycles is a major contributor to the computing requirements. Power consumption of the analog-to-digital converter (ADC) 303 is also increased by 50%. On experimenting, the phase error estimate and the estimate of the timing offset of the analog signal are found to be inaccurate most of the time.
Selection of coefficients of the equalizer in the low power demodulator 300 is performed for reducing a computing rate of the equalizer to minimize power consumption of the low power demodulator 300. An algorithm where a single predetermined equalizer is selected and a timing estimator based on Gardner's algorithm is disclosed below:eT(nT)=Ip(nT)*[I((n+½)T)−I((n−½)T)]+Qp(nT)*[Q((n+½)T)−Q((n−½)T)]
The algorithm is used to estimate the timing offset in the received analog signal. The estimated timing offset is fed back to the interpolator 308 as exemplarily illustrated in FIG. 3, where the interpolator 308 works twice per symbol as shown in the equation below:eC(nT)=Ip(nT)*Q(nT)−I(nT)*Qp(nT)
However, in practice, convergence of the equalizer and proper demodulation of the signal are not always successful. The algorithm above and the interpolator 308 are computationally more intensive. The low power demodulator 300 in the multi-speed Highway Addressable Remote Transducer (HART) (MSH) modem minimizes the number of multiplications needed by in-built algorithms for demodulation of the received HART frequency shift keying (FSK) signal or the received HART coherent 8-ary phase shift keying (C8PSK) analog signal. However, power consumption and cost of implementation of the MSH modem are not reduced. Demodulator structures with configurable filters and oscillators can demodulate the received HART FSK signal or the received HART C8PSK analog signal. However, the power consumption is not low. Furthermore, it is difficult to implement C8PSK modems in application specific integrated circuits (ASICs) that typically implement modems, because the existing C8PSK modem algorithms are too complex to implement in ASICS due to a multi-stage decision making process.
Typically, the Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) modem must perform simultaneous detection of the received analog signal in the frequency shift keying (FSK) protocol, that is, detection of the slower 1200 bits per second Bell 202 based FSK modulation signal, along with the received analog signal in the C8PSK protocol. The simultaneous detection is conventionally implemented by one of many automatic modulation classification (AMC) methods. Many of the AMC methods are computationally intensive and need to be performed at a high sample rate. In the low power demodulator 300 of the multi-speed Highway Addressable Remote Transducer (HART) (MSH) modem exemplarily illustrated in FIG. 3, detection of the analog signal in the FSK protocol is performed and then the low power demodulator 300 is switched to demodulate the analog signal in the C8PSK protocol, which is computationally intensive.
Although modulation is inherently less complex, efficiencies can be achieved in the modulator of the Highway Addressable Remote Transducer (HART) coherent 8-ary phase shift keying (C8PSK) modem too. Hence, to improve power efficiency in the HART C8PSK modem, there is a long felt but unresolved need for modulation and demodulation of the received analog signal to be optimized for power and performance. Moreover, there is a need for a demodulator in the HART C8PSK modem that identifies and adaptively demodulates the received analog signal in the FSK protocol and the C8PSK protocol with low power consumption.